Abstract




 
   

IJE TRANSACTIONS A: Basics Vol. 31, No. 7 (July 2018) 1409-1417    Article in Press

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  AN ACCURATE 2D ANALYTICAL MODEL FOR TRANSCONDUCTANCE-TO-DRAIN CURRENT RATIO (GM/ID) FOR A DUAL-HALO DUAL-DIELECTRIC TRIPLE-MATERIAL CYLINDRICAL-GATE –ALL-AROUND (DH-DD-TM-CGAA) MOSFETS
 
N. Gupta, Janak Kumar B Patel and A.K. Raghav
 
( Received: November 13, 2017 – Accepted: March 09, 2018 )
 
 

Abstract    The dual-halo dual-dielectric Triple-Material Cylindrical-gate-all-around MOSFET offers higher current driving capability, more speed, lower power consumption, excellent immunity against short channel effects and increased device density on the chip. In this paper, an analytical model for the Transconductance-to-Drain Current ratio (TDCR) is developed for a dual-halo dual-dielectric triple-material cylindrical-gate-all-around/Surrounding gate (DH-DD-TM-CGAA/SG) MOSFET based on the surface potential method. The results show that larger value of gm/Id can be obtained in proposed device in comparison to other triple material structures. Moreover the effect of variations in oxide thickness, silicon thickness, channel doping concentration and drain bias are also examined. The effectiveness of the developed gm/Id model is closely agree with the TCAD Silvaco simulation results confirms the validity of the proposed model.

 

Keywords    SCEs, Triple Metal, Dual Dielectric material, Halo Implant, Transconductance

 

چکیده    MOSFET سیلندر گازی دو طرفه-دی الکتریک دوگانه-دی الکتریک دارای توان بالا رانندگی، سرعت بیشتر، مصرف کم انرژی، ایمنی عالی در برابر اثرات کانال کوتاه و افزایش تراکم دستگاه در تراشه است. در این مقاله، یک مدل تحلیلی برای نسبت تراکم به کشیدن جریان (TDCR) برای یک دروازه استوانه ای دروازه دو طرفه / دی الکتریک دو طرفه دیود الکترومغناطیسی در اطراف / محیط اطراف (DH-DD-TM-CGAA / SG) MOSFET بر اساس روش بالقوه سطح. نتایج نشان می دهد که مقدار بزرگتر از gm / Id می تواند در دستگاه پیشنهادی در مقایسه با دیگر ساختارهای مواد سه گانه به دست آید. علاوه بر این اثر تغییرات در ضخامت اکسید، ضخامت سیلیکون، غلظت doping کانال و تعصب تخلیه نیز بررسی شده است. اثربخشی مدل GM / ID توسعه یافته با نتایج شبیه سازی TCAD سیلواکو دقیقا موافق است و اعتبار مدل پیشنهادی را تایید می کند.

References    1.  Park, J. T. and Colinge, J. P., “Multi-gate SOI MOSFETs: device design guidelines”, IEEE Transactions on Electron Devices,  Vol. 49, No. 12, (2002), 2222-2229. 2. Kumar, M. J., Orouji, A. A. and Dhakad, H., “New Dual-Material Surrounding Gate Nanoscale MOSFET: Analytical Threshold-Voltage model”, IEEE Transactions on Electron Devices,  Vol. 53, No. 4, (2006), 920-923. 3. Chiang, T. K., Chen, M. L. and Wang, H. K., “A new Two-dimensional model for Dual Material Surrounding Gate (DMSG) MOSFET’s”, IEEE Conference on Electron Devices and Solid-state Circuits,  Vol. 20, (2007), 597-600. 4. Balamurugan, N. B., Sankaranarayanan, K. and John, M. F., “2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOI MOSFETs”, Journal of Semiconductor Technology and Science,  Vol. 9, No. 2, (2009), 110-116. 5. Niaraki, R., Nobakht, M.,  “A Sub-threshold 9T Static Random-access Memory cell with high write and read ability with bit interleaving capability”, International Journal of Engineering-Transactions B: Applications, Vol. 29, No. 05, (2016), 630-636. 6. Karimi, G. R.,  Shirazi, S. G., “ Ballistic (n,0) carbon    nanotube Field Effect Transistors' I-V Characteristics: A comparison of n=3a+1 and n=3a+2”, International Journal of Engineering-Transactions A: Basics, Vol. 30, No. 04, (2017), 516-522.. 7. Rajendran, K. and Samudra, G. S., “Modeling of transconductance-to-current ratio (gm/ID) analysis on double-gate SOI MOSFETs”, Journal of Semiconductor Technology and Science,  Vol. 15 (2000), 139-144. 8. Kranti, A., Rashmi, Haldar, S. and Gupta, R. S., “Design and Optimization of Vertical Surrounding Gate MOSFETs for Enhanced transconductance-to current ratio (gm/Ids)”, Solid-state Electronics,  Vol. 47, (2003), 153-159. 9. conde, O. A., Sanchez, G., Malo, S. babic and Muci, J., “Drain current and transconductance model for an undoped body asymmetric double gate MOSFET”, Proceedings of international Conference on Solid state and Integrated Circuit Technology, (2006), 1239-1242. 10. Balamurugan, N. B., Sankaranarayanan, K., Amutha, P. and John, M. F., “An Analytical Modeling of Threshold and Subthreshold Swing on Dual Material Surrounding Gate Nanoscale MOSFETs for high speed Wireless Communication”, Journal of Semiconductor Technology and Science,  Vol. 8, No. 3, (2008), 221-226. 11. Ghosh, P., Haldar, S. and Gupta, R. S., “Analytical modeling and simulation for dual metal gate stack architecture cylindrical/surrounded gate MOSFET”, Journal of Semiconductor Technology and Science,  Vol. 12, No. 4, (2012), 458-463. 12. Wang, H. K., Chiang, T. K. and Lee, M. S., “A new two dimensional analytical threshold voltage model for short channel triple material surrounding gate MOSFETs”, Japanese Journal of Applied Physics, Vol. 51, No. 5, (2012), 1-5. 13. Dhanaselvam, P. S. and Balamurugan, N. B., “A 2D transconductance and sub-threshold behavior model for triple material surrounding gate MOSFETs”, Microelectronics Journal,  Vol. 44, No. 12, (2013), 1159-1164. 14. Dubey, S., Santra, A., Saramekala, G., Kumar, M. and Tiwari, P. K., “An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs”, IEEE Transactions on Nanotechnology,  Vol. 12, No. 5, (2013), 766-774. 15. Dhanaselvam, P. S., Chakaravarthi, G. C. V., Ramesh, R. P. and Balamurugan, N. B., “A 2D analytical modeling of single halo triple material surrounding gate MOSFET”, Journal of Electrical Engineering & Technology,  Vol. 9, No. 4, (2014), 1355-1359. 16. Sharifi, M. J., Adibi, A., “Semiconductor device simulation by a new method of solving poission, laplace and schrodinger equations”, International Journal of Engineering, Vol. 13, No. 1, (2000), 89-94. 17. Shafiabadi, M. and Mehrabani, Y. S., "Symmetrical, low-power, and high-speed 1-bit full adder cells using 32nm carbon nanotube field-effect transistors technology", International Journal of Engineering-Transactions A: Basics, Vol. 28, No. 10, (2015), 1447-1452. 18. ATLAS device simulator Silvaco International manual, (2015).





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