Abstract




 
   

IJE TRANSACTIONS B: Applications Vol. 30, No. 11 (November 2017) 1598-1607    Article in Press

PDF URL: http://www.ije.ir/Vol30/No11/B/32.pdf  
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  DESIGN AND PERFORMANCE ANALYSIS OF 7-LEVEL DIODE CLAMPED MULTILEVEL INVERTER USING MODIFIED SVPWM TECHNIQUES
 
L. R. Chintala, S. K. Peddapelli and S. Malaji
 
( Received: March 03, 2017 – Accepted: July 07, 2017 )
 
 

Abstract    In this paper, a 7-level Diode Clamped Multilevel Inverter (DCMLI) is simulated with three different carrier PWM techniques. Here, carrier based Sinusoidal Pulse Width Modulation (SPWM), Third Harmonic Injected Pulse Width Modulation (THIPWM) and Modified Carrier-Based Space Vector Pulse Width Modulation (SVPWM) are used as modulation strategies. These modulation strategies include Phase Disposition Technique (PD), Phase Opposition Disposition Technique (POD), and Alternate Phase Opposition Disposition Technique (APOD). In all the modulation strategies triangular carrier and trapezoidal triangular carrier signlas are compared with refrence signal and control pulses are generated. The detailed analysis of the results has been presented and compared with experimental results in terms of fundamental component of output voltage and % of THD.

 

Keywords    DCMLI, PDSVPWM, PODSVPWM, APODSVPWM.

 

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