1. Abadir Magdy S., and Hassan K. Reghbati. "Functional testing of semiconductor random access memories." ACM Computing Surveys (CSUR) 15.3 (1983), page no. 175-198. 2. Bushnell Michael, and Vishwani D. Agrawal. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Vol. 17. Springer Science & Business Media, 2000. 3. Caşcaval Petru and Doina Caşcaval. "March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories." Microelectronics Journal 41.4 (2010) , page no. 212-218. 4. Chandra, Anshuman, and Krishnendu Chakrabarty. "Combining low-power scan testing and test data compression for system-on-a-chip." Proceedings of the 38th annual Design Automation Conference. ACM, 2001. 5. Cheung Hugo, and Sandeep K. Gupta. "A BIST methodology for comprehensive testing of RAM with reduced heat dissipation." Test Conference, 1996. Proceedings, International. IEEE, 1996. 6. Dilillo Luigi, Girard P., Pravossoudovitch S., Virazel A. and Hage-Hassan M. B. "Data retention fault in sram memories: analysis and detection procedures." VLSI Test Symposium, 2005. Proceedings. 23rd IEEE. IEEE, 2005. 7. Gadde Priyanka, and Mohammed Niamat. "FPGA memory testing technique using BIST." Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on. IEEE, 2013. 8. Kim Yun-Hong, et al. "An Efficient Test Procedure for Functional Faults in Semiconductor Random Access Memories." Journal of Circuits, Systems, and Computers 1.02 (1991), page no. 229-238. 9. Kim Von-Kyoung, and Tom Chen. "On comparing functional fault coverage and defect coverage for memory testing." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 18.11 (1999), page no. 1676-1683. 10. Kumar K. Sathish, Shravan Kaundinya, and Santanu Chattopadhyay. "Particle swarm optimization based scheme for low power march sequence generation for memory testing." Test Symposium (ATS), 2010 19th IEEE Asian. IEEE, 2010. 11. Li, Jin-Fu, Cheng K. L., Huang C. T. and Wu C. W. "March-based RAM diagnosis algorithms for stuck-at and coupling faults." Test Conference, 2001. Proceedings. International. IEEE, 2001. 12. Niamat M. Y., D. M. Nemade, and M. M. Jamali. "Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs." Microelectronic engineering 84.2 (2007), page no. 194-203. 13. Nicolici, Nicola, and Bashir Al-Hashimi. Power-constrained testing of VLSI circuits. Boston, MA: Kluwer Academic Publishers, 2003. 14. Papachristou Christos A., and Narendar B. Sahgal. "An improved method for detecting functional faults in semiconductor random access memories." Computers, IEEE Transactions on 100.2 (1985), page no. 110-116. 15. G. Rajesh Kumar and K. Babulu. "A Novel Architecture for Scan Cell in Low Power Test Circuitry." Procedia Materials Science 10 (2015), page no. 403-408. 16. Suk, Dong S., and Sudhakar M. Reddy. "A march test for functional faults in semiconductor random access memories." Computers, IEEE Transactions on100.12 (1981), page no. 982-985. 17. Vardanian Valery A., and Yervant Zorian. "A march-based fault location algorithm for static random access memories." On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International. IEEE, 2002. 18. Y. Zorian, Testing the monster chip, IEEE Spectrum, 36(7), July 1999, page no. 54-60. 19. Juneja, K., N. P. Singh, and Y. Sharma. "High-performance and low-power clock branch sharing pseudo-NMOS level converting flip-flop." International Journal of Engineering-Transactions C: Aspects 26.3 (2012): 315.